RE: https://mendeddrum.org/@fanf/116090957426748922
30-year-old analysis of RISC vs CISC still reads well!
though it's fun to see which RISCisms have died out, such as "Do NOT support arbitrary alignment of data for loads/stores"
@regehr an old colleague of mine once said "these days they're all MISC architectures."
@regehr These days I see this most often as "people who hate wintel wanting to claim ARM is better because RISC" despite for most of the period Intel just making better parts than available from any of the ARM vendors. Being like 5 years ahead on fabs vs. everyone else was a Big Deal.
I hear this discussion less now that ARM parts competitive with Intel are out as of 2020. If anything, these days I hear the discussion in the opposite direction: Windows people blaming Apple's slight processor lead for all of Windows problems and expecting Snapdragon to fix it. (Snapdragon X Elite looks like an interesting part but I refuse to buy one until I see at least MS treat it as a first class target. I bought 2 Windows on ARM devices that are paperweights and I won't get burned like that a 3rd time. It's depressing to see people talk about Windows on ARM like it's the "new hotness" when Windows on ARM is *older* than macOS on ARM!)
although I guess the alignment story is a bit more complicated than that. modern x86 vector extensions sometimes require alignment, and AArch64 allows (but does not require) support for unaligned accesses
@regehr And then there's AltiVec's memory instructions which IIRC would clear the last four bits of the calculated address before actually hitting memory so if you pass it misaligned address it'll appear to work, but not in the way you think it is...
@regehr and usually unaligned loads that straddle a cache line, or especially page, boundary still carry a significant cost. so sticking to natural alignment avoids ever dealing with those cliffs
@regehr Feels like in modern processors separating memory operations into its own separate class from the "pure function" instructions is the biggest win of the classic RISC approach; even transgressors like x86 doesn't do it as hard as, say, VAX
Like nowadays computations can get so complicated (see e.g SIMD or AES round functions) yet as long as it stays "pure" it doesn't seem to impact performance too much...
Though then again, I'm no microarchitect~
@regehr okay but that's because unaligned stores are fucking awesome for optimisation
